1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more specifically, it relates to a semiconductor device comprising a capacitor and a method of fabricating the same.
2. Description of the Prior Art
In recent years, high integration and refinement are increasingly required to a semiconductor device, particularly a semiconductor memory device such as a DRAM (dynamic random access memory). FIG. 114 is a typical plan view showing a part of a memory cell region of a conventional DRAM. Referring to FIG. 114, the memory cell region of the conventional DRAM comprises a capacitor including a field-effect transistor and capacitor lower electrodes 1170a and 1170b, word lines 1043a, 1043b, 1043e and 1043f and a bit line 1174. The field-effect transistor is formed by the word lines 1043a and 1043e serving as gate electrodes and an active region 1039 serving as a source/drain region. In more concrete terms, the active region 1039 is formed in a major surface of a semiconductor substrate, and the word lines 1043a, 1043b, 1043e and 1043f are formed on the major surface of the semiconductor substrate. A first interlayer isolation film (not shown) is formed on the word lines 1043a, 1043b, 1043e and 1043f and the major surface of the semiconductor substrate. The bit line 1174 is formed on the first interlayer isolation film substantially perpendicularly to the word lines 1043a, 1043b, 1043e and 1043f. A second interlayer isolation film (not shown) is formed on the bit line 1174 and the first interlayer isolation film. The capacitor lower electrodes 1170a and 1170b are formed on the second interlayer isolation film. The bit line 1174 is electrically connected with the active region 1039 through a contact hole 1049. The capacitor lower electrodes 1170a and 1170b are electrically connected with single ones of source/drain regions of the field-effect transistor in the active region 1039 through contact holes 1038a and 1038b respectively. FIG. 115 is a sectional view of the memory cell region of the DRAM taken along the line 500-500 in FIG. 114.
FIG. 115 is a sectional view showing the section taken along the line 500-500 in FIG. 114 and a section of a peripheral circuit region of the DRAM. Referring to FIG. 115, source/drain regions 1201a and 1201b of the field-effect transistor are formed on the active region 1039 enclosed with a trench isolation oxide film 1040 in the memory cell region of the DRAM. A gate electrode 1043a is formed on a channel region held between the pair of source/drain regions 1201a and 1201b through a gate insulating film 1042a. A silicon nitride film 1044a is formed on the gate electrode 1043a. The gate electrode 1043a consists of n-type doped polysilicon. Side walls 1046a and 1046b consisting of silicon nitride films are formed on side surfaces of the gate electrode 1043a and the silicon nitride film 1044a. A non-doped silicon oxide film 1047 is formed on the side walls 1046a and 1046b, the silicon nitride film 1044a and a major surface of a semiconductor substrate 1001. A gate electrode 1043b is formed on the trench isolation oxide film 1040 through a gate insulating film 1042b. A silicon nitride film 1044b is formed on the gate electrode 1043b. Side walls 1046c and 1046d consisting of silicon nitride films are formed on side surfaces of the gate electrode 1043b and the silicon nitride film 1044b. The non-doped silicon oxide film 1047 is formed on the side walls 1046c and 1046d and the silicon nitride film 1044b. A first interlayer isolation film 1048 is formed on the non-doped silicon oxide film 1047. The contact hole 1049 is formed by partially removing the first interlayer isolation film 1048 and the non-doped silicon oxide film 1047 by etching. A doped polysilicon film 1052 is formed in the contact hole 1049 and on the first interlayer isolation film 1048. A refractory metal silicide film 1053 is formed on the doped polysilicon film 1052. The doped polysilicon film 1052 and the refractory metal silicide film 1053 form the bit line 1174. A silicon nitride film 1054 is formed on the refractory metal silicide film 1053. Side walls 1055a and 1055b consisting of silicon nitride films are formed on side surfaces of the silicon nitride film 1054, the refractory metal silicide film 1053 and the doped polysilicon film 1052. A second interlayer isolation film 1037 is formed on the first interlayer isolation film 1048, the side walls 1055a and 1055b and the silicon nitride film 1054. The first and second interlayer isolation films 1048 and 1037 are partially removed, thereby forming the contact hole 1038a for electrically connecting the capacitor lower electrode 1170a with one of the source/drain regions 1201a and 1201b. A plug 1057 consisting of doped polysilicon is formed in the contact hole 1038a. The capacitor lower electrode 1170a is formed in the contact hole 1038a and on the second interlayer isolation film 1037. The capacitor lower electrode 1170a has a cylindrical structure, in order to ensure the capacitance of the capacitor with a small occupied area. A dielectric film 1150 is formed on the capacitor lower electrode 1170a and the second interlayer isolation film 1037. A capacitor upper electrode 1151 is formed on the dielectric film 1150. A third interlayer isolation film 1205 is formed on the capacitor upper electrode 1151.
The peripheral circuit region is provided with the field-effect transistor and a wiring layer 1202 which are elements forming peripheral circuits. Source/drain regions 1201d and 1201e are formed on the major surface of the semiconductor substrate 1001. Gate electrodes 1043c and 1043d are formed on channel regions which are adjacent to the source/drain regions 1201d and 1201e through gate insulating films 1042c and 1042d respectively. Silicon nitride films 1044c and 1044d are formed on the gate electrodes 1043c and 1043d. Side walls 1046e to 1046g consisting of silicon nitride films are formed on side surfaces of the gate electrodes 1043c and 1043d and the silicon nitride films 1044c and 1044d. The non-doped silicon oxide film 1047 is formed on the major surface of the semiconductor substrate 1001, the silicon nitride films 1044c and 1044d and the side walls 1046e to 1046g. The first interlayer isolation film 1048 is formed on the non-doped silicon oxide film 1047. The first interlayer isolation film 1048 is partially removed, thereby forming contact holes 1050 and 1051. The doped polysilicon film 1052 is formed on the first interlayer isolation film 1048 and in the contact holes 1050 and 1051. The refractory metal silicide film 1053 is formed on the doped polysilicon film 1052. The doped polysilicon film 1052 and the refractory metal silicide film 1053 form the wiring layer 1202 in the peripheral circuit region. A silicon nitride film 1203 is formed on the refractory metal silicide film 1053. Side walls 1204a and 1204b consisting of silicon nitride films are formed on side surfaces of the silicon nitride film 1203, the refractory metal silicide film 1053 and the doped polysilicon film 1052. The second interlayer isolation film 1037 is formed on the first interlayer isolation film 1048, the silicon nitride film 1203 and the side walls 1204a and 1204b. The dielectric film 1150 of the capacitor extending from the memory cell region is formed on the second interlayer isolation film 1037. The capacitor upper electrode 1151 is formed on the dielectric film 1150. The third interlayer isolation film 1205 is formed on the second interlayer isolation film 1037 and the capacitor upper electrode 1151.
FIG. 116 illustrates a modification of the memory cell region of the conventional RAM shown in FIG. 115. This modification has a capacitor lower electrode 1092 which is in the form of a thick film. The structure of this modification is substantially identical to that of the conventional DRAM shown in FIG. 115, except the shape of the capacitor lower electrode 1092.
As shown in FIG. 115 or 116, the capacitor lower electrode 1170a or 1092 is formed to vertically extend in the memory cell region of the conventional DRAM, in order to ensure the capacitance of the capacitor while facilitating high integration and refinement. Thus, the capacitance required to the capacitor can be ensured while reducing the occupied area of the capacitor lower electrode 1170a or 1092 in the memory cell region. However, such vertical extension of the capacitor lower electrode 1170a or 1092 in the memory cell region results in extreme difference between the vertical positions of the upper surface of the third interlayer isolation film 1205 in the memory cell region and the peripheral circuit region. In general, a wiring layer consisting of aluminum or the like is formed on the third interlayer isolation film 1205. In a photolithographic step for forming this wiring layer, however, no sufficient focal allowance for photolithography can be attained due to the step on the upper surface of the third interlayer isolation film 1205 in the memory cell region and the peripheral circuit region. Thus, the pattern of the wiring layer formed on the third interlayer isolation film 1205 is so blurred that the wiring layer is disconnected or shorted. Consequently, the semiconductor device is disadvantageously reduced in reliability.
In the peripheral circuit region of the conventional DRAM, further, contact holes 1144 and 1135 are formed in order to electrically connect the wiring layer 1202 and the capacitor upper electrode 1151 in the peripheral circuit region with a wiring layer (not shown) consisting of aluminum or the like formed on the third interlayer isolation film 1205, as shown in FIG. 117. While the contact holes 1144 and 1135 are generally simultaneously formed in the same etching step, the capacitor upper electrode 1151 is excessively etched on a bottom portion of the contact hole 1135 until the contact hole 1144 reaches the wiring layer 1202, due to the difference between the depth positions of the capacitor upper electrode 1151 and the wiring layer 1202 formed in the peripheral circuit region. Consequently, the contact hole 1135 may pass through the capacitor upper electrode 1151 and the dielectric film 1150, as shown in FIG. 117. Further, the elements of the peripheral circuit region such as the wiring layer 1202 and the field-effect transistor damaged by the etching for forming the contact hole 1135. Consequently, the reliability of the semiconductor device is so reduced that the same cannot stably operate or causes a malfunction.